This topic covers the basic concepts of computer architecture and organization, including the role of hardware and software in computing systems, the von Neumann architecture, and the relationship between hardware and software components.
Introduction to Computer Architecture & Organization
(A concise, easy‑to‑read study guide)
| Aspect | Definition |
|---|---|
| Architecture | The visible attributes of a system that affect programming: instruction set, memory hierarchy, I/O mechanisms, addressing modes, and system‑level performance goals. |
| Organization | The implementation details that realize the architecture: datapath design, control logic, micro‑operations, pipelines, cache structures, and physical interconnects. |
| Key Idea | Architecture = what the computer does. Organization = how it does it. |
(Each lower level must satisfy the specifications of the level above it.)
| Category | Examples | Why It Matters |
|---|---|---|
| Data Types | Integer, floating‑point, SIMD vectors, packed BCD | Determines operand size & precision. |
| Instruction Formats | R‑type, I‑type, J‑type (MIPS); VEX prefix (x86) | Defines encoding, length, and decoding complexity. |
| Addressing Modes | Register, immediate, base+offset, PC‑relative, indexed | Impacts code density and compiler optimization. |
| Control Flow | Branch, jump, call/return, conditional move | Influences pipeline hazards & branch prediction. |
| Privilege Levels | User, kernel (ring 0), hypervisor | Provides security & isolation. |
| Exceptions & Interrupts | Fault, trap, abort, system call | Enables OS interaction and error handling. |
Common ISAs: x86‑64, ARMv8‑A, RISC‑V, MIPS, PowerPC.
| Component | Function |
|---|---|
| ALU (Arithmetic‑Logic Unit) | Executes integer/floating‑point arithmetic, logical ops, shifts. |
| Registers | Fast, on‑chip storage for operands, results, control info (e.g., PC, IR, status flags). |
| Control Unit | Generates control signals; can be hardwired or microprogrammed. |
| Memory Hierarchy | Registers → L1/L2/L3 caches → Main memory (DRAM) → Secondary storage. |
| I/O Subsystem | Device controllers, buses, interrupt handling. |
| Clock | Global timing reference; defines cycle time (period). |
[Instruction Fetch] → [Decode] → [Execute] → [Memory Access] → [Write‑Back]
| | | | |
PC → IR Control ALU/FPU Data Cache Register File
The classic 5‑stage pipeline (IF, ID, EX, MEM, WB) is the foundation of many modern CPUs.
| Level | Typical Size | Latency (cycles) | Purpose |
|---|---|---|---|
| Registers | 32–256 KB (total) | 1 |